DPLA: much more efficient than FPGA

The Reconfigurable
Computing Paradox (RC Paradox):
much more area-inefficient than microprocessors, FPGAs are excellent
accelerators. It’s because of the paradigm shift: away from von Neumann. For
some special purpose applications much more area-efficient accelerators like
PLAs can be used: but only for canonical Boolean expressions. To accelerate a
Mead-&-Conway design rule check (PISA
project) we would have needed 256 FPGAs under Moore’s law of the mid’ 80ies. For
a PLA-based solution we needed only a single “**DPLA**”
designed by us and manufactured by the MPC infrastructure of the
E.I.S. project (also see
here). We obtained a speed-up factor of 15.000 –
more than 15 years earlier
than the
RC speed-up culture.^{th}
Anniversary Paper.

The DPLA was implemented as a special kind of FPGA, called FP**C**A.

This acronym stands for **F**ield-**P**rogrammable **C**anonical Logic **A**rray.